Homework and project assignments will be posted here
First Homework Assignment (pdf format). Due: Thursday, January 27, 2011, in class.
Third
Homework Assignment, Due Thursday, Feb. 17 in class
Fourth
Homework Assignment, Due Thursday, Feb. 24, in class
Fifth
Homework Assignment, Due Thursday, March 31, in class
Second Verilog Project. Due dates: Thurs. April 7, Tues.
April 12, Thurs. April 14, Tues. April 19
A short (12 entry) trace file to
test your two-way set associative cache can be found here. This file is
commented to show the expected behavior of the two-way cache. A transcript is
also provided that shows the result of running this trace file for a correct
implementation of the two-way cache. You may find this trace file to be useful
for debugging your design (turn on verbose and dbg
modes to see how your cache is functioning versus expected behavior).
A correct solution to the cache
controller design for Part 2 of the Second Verilog
Project can be found here.
Students who were not able to get their cache to work properly for Part 2 of
the project may use this version of the controller to complete Items 2 and 3 of
the Part 2 submission requirements. These may be submitted for partial credit
by no later than 11:59 p.m. on Friday, April 15. This cache controller may also
be used as the starting point for your implementation of Part 4 of the project.
Sixth
Homework Assignment, Due Tuesday, May 3, in class