HPCA News for Spring, 2011: 

1/20/11: The first homework assignment has been posted. The Due date is: Thursday, January 27, in class.

1/21/11: As announced, there will be no class meeting on Tues. January 25. A streaming video lecture has been prerecorded to cover the material for this class period. Please be sure to view the recorded lecture prior to the next regular class meeting on Thurs. Jan. 27. The lecture is available via the following link:

https://globalcampus.uiowa.edu/play_recording.html?recordingId=1262309408949_1295560668859

Clicking on this link should take you directly to the lecture. The recorded lecture uses a web-based product called Elluminate Live. In order to view the lecture, your computer must have Java Web Start installed. If you have any problems with accessing or using Elluminate Live to view the lecture, please consult the University’s support site:

http://its.uiowa.edu/support/collaboration/webconferencing.shtml

1/21/11: Professor Kuhl will NOT be available for Office Hours on Tuesday, January 25. However, he will hold additional Office Hours from 1:30-3:00 p.m. on Wednesday, January 26.

11/27/11 All students will need an engineering (CSS) computer account to access the Verilog environment, which is hosted on CSS Linux systems.  If you do not already have an active CSS account, one has automatically been generated for you.  The user-ID for this account will be your Hawk-ID.  To get the initial account password, go to the following site:

http://css.engineering.uiowa.edu/getpassword

Enter your Hawk-ID and Hawk-ID password as directed to retrieve your CSS password.  You will be required to change this password after your initial login to a CSS system. If you have had a CSS account at some point in the past, the initial password may no longer be valid.  If you cannot log-in using the specified password, please contact the CSS Office in 1256 SC and ask them to reset your password.

There are two ways to do a GUI login to the CSS Linux environment:

  1) Directly log into one of the Linux workstations located in the CSS labs on the first floor of the Seamans Center

  2)  Log into a Windows workstation in one of the CSS labs and use NOMACHINE to log into the Linux environment.  From the Windows Start/All Programs menu, you should see an entry titled "NX Client for Windows".  Clicking this entry will launch the necessary NOMACHINE client.

You can also to a terminal (command-line only) login to the CSS Linux environment using SSH, SecureCRT, etc.  The hostname is:  login.engineering.uiowa.edu   SSH2 is required. When running a Verilog simulation from the command-line interface, be sure to specify the -c option, i.e. vsim -c <top-level module name>

02/03/11: As announced in class, there will not be a regular lecture on Tuesday, February 8. A streaming video lecture has been prerecorded and is available at the following link:

https://globalcampus.uiowa.edu/play_recording.html?recordingId=1262310009078_1296773843644

Please be sure to view this lecture prior to the next regular class meeting on Thursday, Feb. 10. For additional information on using Elluminate see the earlier note above.

02/03/11: Prof. Kuhl will NOT be available for office hours on Tuesday, Feb. 8.

02/11/11: The third homework assignment has been posted. Due date is Thursday, Feb. 17, in class.

03/04/11: A quick scan of the submissions for Part 2 of the first Verilog Project reveals that a number of students did not successfully complete the assignment.  Since it is highly unlikely that you will be successful with Part 3 of the project without first completing Part 2, I urge all students who have not completed Part 2 to continue to work on this portion of the project before moving on to Part 3.  We will continue to accept submissions/resubmissions of Part 2, with a 10% late penalty, up until the final project submission date (Tuesday, March 8, 11:59 p.m.).  I will hold extra office hours today (Friday, March 4) from 1:30-3:30 p.m. and on Monday, March 7 between 9:00 a.m. and 11:00 a.m. to provide assistance with any project-related issues.

A correct implementation of Part 2 should result in 86 branch mispredictions for the matrix multiply program.

04/12/11: For Parts 3 and 4 of the Second Verilog Project: A short (12 entry) trace file to test your two-way set associative cache can be found here. This file is commented to show the expected behavior of the two-way cache. A transcript is also provided that shows the result of running this trace file for a correct implementation of the two-way cache. You may find this trace file to be useful for debugging your design (turn on verbose and dbg modes to see how your cache is functioning versus expected behavior).

04/13/11: A correct solution to the cache controller design for Part 2 of the Second Verilog Project can be found here. Students who were not able to get their cache to work properly for Part 2 of the project may use this version of the controller to complete Items 2 and 3 of the Part 2 submission requirements. These may be submitted for partial credit by no later than 11:59 p.m. on Friday, April 15. This cache controller may also be used as the starting point for your implementation of Part 4 of the project.

04/26/11: The sixth, and final, homework assignment has been posted. The due date is Tuesday, May 3, in class